Lesson 1Microcontroller families comparison: AVR, PIC, ARM Cortex-M (M0/M3/M4) — performance, peripherals, and ecosystemThis section compares major microcontroller families. You will examine AVR, PIC, and ARM Cortex-M devices in terms of performance, peripherals, tools, ecosystem, cost, and suitability for communication-centric embedded designs.
AVR architecture, strengths, and use casesPIC families and typical application domainsARM Cortex-M cores: M0, M3, and M4 featuresEcosystem, tools, and community supportPeripherals, memory, and performance scalingCost, availability, and long-term lifecycleLesson 2Basic firmware safety: watchdog timer usage, fault reporting, and robust reset strategiesThis section focuses on basic firmware safety mechanisms. You will configure watchdog timers, design safe reset and recovery flows, implement fault reporting, and ensure that unexpected hangs or corrupt states are detected and handled.
Watchdog timer configuration and feedingDetecting and handling lockups and dead loopsBrown-out, POR, and external reset handlingStoring reset cause and fault contextNonvolatile logging of critical failuresSafe restart and degraded operation modesLesson 3GPIO and peripheral budgeting: ADC channels, UART/SPI/I2C ports, timers, interrupts and DMA planningThis section covers mapping GPIOs and on-chip peripherals to system needs. You will plan ADC channels, serial ports, timers, interrupts, and DMA usage to avoid conflicts, support future expansion, and meet real-time constraints.
Creating a complete signal and pin inventoryMapping ADC channels to sensors and referencesAllocating UART, SPI, and I2C for peripheralsTimer allocation for PWM, capture, and timebaseInterrupt priority and nesting considerationsPlanning DMA channels for high data throughputLesson 4Essential MCU hardware choices: supply voltage, clock source (internal RC, crystal, external oscillator), and power domainsThis section guides key MCU hardware choices. You will evaluate supply voltage ranges, clock source options, and power domains, considering performance, noise, analogue accuracy, and compatibility with sensors, radios, and external logic.
Selecting core supply voltage and regulatorsI/O voltage levels and level shifting needsInternal RC oscillator pros and consCrystal and external oscillator selectionSeparating analog and digital power domainsDecoupling and ground layout implicationsLesson 5Clocking and timing: selecting clock source, configuring system tick, low-power modes and wake sourcesThis section explains clock tree and timing configuration. You will select clock sources, set PLLs, configure system tick, and design low-power modes and wake sources while meeting timing, jitter, and power consumption requirements.
Clock tree overview and configuration stepsPLL, prescalers, and frequency trade-offsSystem tick configuration and timekeepingTimer usage for delays and schedulingLow-power sleep and stop mode selectionWakeup sources and latency managementLesson 6ADC driver design: sampling sequence, oversampling, averaging, and conversion timingThis section details ADC driver design for accurate measurements. You will plan sampling sequences, configure triggers, apply oversampling and averaging, manage conversion timing, and minimise noise through hardware and firmware techniques.
ADC reference selection and calibrationChannel sequencing and scan configurationSampling time and trigger source selectionOversampling, averaging, and filteringDMA-based ADC data acquisitionMitigating noise and crosstalk in readingsLesson 7Embedded power management: sleep modes, brown-out detection, RTC for wakeups, and battery considerationsThis section addresses embedded power management strategies. You will use sleep modes, brown-out detection, and RTC-based wakeups, and consider battery chemistry, capacity, and lifetime for reliable low-power communication systems.
Sleep mode selection and entry criteriaRTC configuration for timed wake eventsBrown-out detection thresholds and actionsMeasuring and budgeting average currentBattery chemistry and discharge behaviorDesigning for long battery life and safetyLesson 8Firmware architecture and flow: boot, peripheral init, sensor read routine, error handling, data formatting, comms schedulingThis section presents overall firmware structure from reset to normal operation. You will design boot flow, peripheral initialization, sensor read loops, error handling paths, data formatting, and communication scheduling for deterministic behaviour.
Boot sequence and startup code overviewPeripheral and middleware initialization orderDesigning periodic sensor read tasksCentralized error handling and logging pathsData formatting, scaling, and unit handlingCooperative scheduling and main loop designLesson 9Communication driver design: UART, SPI, I2C stacks; polling vs interrupt vs DMA approachesThis section explains how to design reusable UART, SPI, and I2C drivers. You will compare polling, interrupt, and DMA methods, define driver APIs, handle errors and timeouts, and integrate drivers into higher-level protocol stacks.
Layered architecture for serial driversUART driver: framing, buffering, and flow controlSPI driver: modes, chip select, and throughputI2C driver: addressing, arbitration, and retriesPolling versus interrupt-driven transfersDMA-based transfers and ring buffer design
