Chip Design Course
Gain complete expertise in chip design from RTL development to final layout. Create efficient SensorCtrl RTL blocks, manage mixed-signal handshakes with ADCs, ensure robust verification using self-checking testbenches and assertions, and understand the full RTL-to-GDSII process including timing closure, low-power strategies, and reset mechanisms applied in professional semiconductor projects.
flexible workload of 4 to 360h
valid certificate in your country
What will I learn?
This course offers a structured journey from RTL coding to silicon-ready chip blocks. You will master analog-digital interfaces including ADC protocols, clock domain crossings, and metastability handling. Progress to physical design essentials, timing optimisation, and power-saving methods. Develop proficient Verilog or VHDL code for SensorCtrl modules, craft reliable testbenches, implement assertions, and achieve verification coverage targets through a concise, hands-on syllabus.
Elevify advantages
Develop skills
- Design SensorCtrl RTL efficiently with comparator, buffer, and register functions.
- Implement mixed-signal links for ADC data streams, clock signals, and I/O level shifting.
- Excel in verification by developing self-checking testbenches, assertions, and coverage plans.
- Navigate RTL-to-GDSII workflow from synthesis through to final signoff stages.
- Optimise low-power designs using clock gating, reliable resets, and initialisation sequences.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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