VLSI Physical Design Course
This course guides you through VLSI physical design process using a 32-bit ALU block, teaching floorplanning, placement, clock tree synthesis, routing, power integrity with IR drop control, timing closure techniques, and comprehensive signoff checks including STA, DRC, LVS, and reliability verification to produce high-performance chips ready for fabrication in advanced technology nodes.
flexible workload of 4 to 360h
valid certificate in your country
What will I learn?
Gain practical skills in VLSI physical design from RTL handoff to tapeout, covering floorplanning, macro and IO placement, power grid setup, IR drop management, placement optimisation, clock tree synthesis, routing, and timing closure for a 32-bit pipelined ALU, along with signoff checks like STA, DRC, LVS, extraction, reliability analysis, and GDSII preparation for efficient chip manufacturing.
Elevify advantages
Develop skills
- Handle RTL to netlist transition with import, checks, and clean synthesis.
- Excel in floorplanning including macros, IO, power grid, and CMOS hierarchy.
- Optimise placement and CTS for congestion handling and 500 MHz clocks.
- Ensure power integrity via IR drop analysis, decap insertion, and density limits.
- Achieve signoff readiness with STA, DRC, LVS, reliability, and GDSII delivery.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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