VLSI Physical Design Course
This course provides hands-on training in VLSI physical design, covering the full flow from RTL to tapeout for a 32-bit pipelined ALU, including floorplanning, placement, clock tree synthesis, routing, timing optimization, and signoff processes to ensure reliable IC production.
from 4 to 360h flexible workload
valid certificate in your country
What will I learn?
This VLSI Physical Design Course offers a quick, hands-on route from RTL handover to tapeout. You will learn floorplanning, macro and IO placement, power grid setup, IR drop management, component placement, clock tree synthesis, routing, and timing optimisation for a 32-bit pipelined ALU. Gain expertise in signoff processes like static timing analysis, design rule checks, layout versus schematic, extraction, reliability verification, and final GDSII outputs to produce reliable, manufacturable integrated circuits.
Elevify advantages
Develop skills
- RTL to netlist handover: importing, basic checks, and preparing clean synthesis results.
- Floorplanning skills: handling macros, IOs, power grids, and physical hierarchy in CMOS technology.
- Placement and clock tree synthesis: managing congestion in placement and building strong 500 MHz clock networks.
- Power reliability practices: controlling IR drop, planning decoupling capacitors, and adhering to current density standards.
- Signoff assurance: performing static timing analysis, DRC/LVS verification, reliability assessments, and preparing fabrication-ready GDSII files.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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