Lesson 1Backup power options: supercapacitors, UPS, battery-backed RTC — sizing and use casesDetails backup power strategies using supercapacitors, UPS modules, and battery‑backed RTCs, including sizing calculations, charge management, data‑flush timing, and typical use cases such as graceful shutdown and short power interruptions.
Use cases for short‑term backup powerSupercapacitor selection and sizing mathEmbedded UPS modules and charger designBattery‑backed RTC and timekeepingCoordinating backup with firmware shutdownLesson 2Robust power design: input protection, transient suppression (TVS diodes), filtering, isolation, and bulk capacitanceFocuses on robust power input design, including fusing, reverse polarity and overvoltage protection, transient suppression with TVS diodes, LC and RC filtering, galvanic isolation, and bulk capacitance placement for stable operation.
Input fusing, inrush, and reverse polarityTVS diodes and surge protection choicesLC, RC, and common‑mode input filteringIsolation topologies and safety spacingBulk capacitance sizing and placementLesson 3Industrial I/O and interface hardware: isolated UART/RS-485 transceivers, isolated CAN PHYs, Ethernet PHYs with magnetics, ADC front ends for 4–20mAExamines industrial I/O hardware, including isolated UART and RS‑485, isolated CAN PHYs, Ethernet PHYs with magnetics, and 4–20 mA ADC front ends, focusing on isolation, EMC robustness, protection, and field wiring constraints.
Isolated UART and RS‑485 transceiver designIsolated CAN PHYs and bus protectionEthernet PHYs, magnetics, and layout rules4–20 mA current loop input front endsSurge, ESD, and overvoltage protectionLesson 4Memory and persistent storage choices: flash, eMMC, SD cards, wear-leveling, and filesystem options (journaling, log-structured)Explores embedded nonvolatile memory options, comparing NOR/NAND flash, eMMC, and SD cards, with emphasis on endurance, wear‑leveling behavior, performance, and filesystem choices such as journaling and log‑structured designs for reliability.
NOR vs NAND flash characteristicseMMC architecture and reliability modesSD card selection for embedded systemsWear‑leveling, endurance, and write patternsJournaling and log‑structured filesystemsData integrity, power‑fail safe techniquesLesson 5Hardware watchdog circuits and supervisory ICs, programmable supervisors, and reset sourcesDescribes hardware watchdogs, supervisor ICs, and reset sources, explaining how to monitor supply rails and system health, configure programmable supervisors, and design reliable reset trees that avoid lockups and unintended resets.
Internal vs external watchdog strategiesWindowed watchdogs and fault coverageVoltage supervisors and reset generatorsProgrammable supervisors and sequencingDesigning robust reset distribution treesLesson 6Brown-out detection, reset strategies, and power sequencing best practicesCovers brown‑out detection, reset timing, and power sequencing best practices, including threshold selection, hysteresis, controlled ramp‑up, and coordination between multiple rails to prevent latch‑up, corruption, and undefined states.
Brown‑out thresholds and hysteresis designReset timing, delays, and glitch filteringMulti‑rail sequencing order and timingPreventing latch‑up and undefined statesTesting brown‑out and recovery behaviorLesson 7Selecting a main processing platform: microcontroller vs single-board computer — tradeoffs and decision criteriaAnalyzes how to choose between microcontrollers and single‑board computers, comparing performance, power, real‑time behavior, OS support, connectivity, security, and lifecycle, and defining decision criteria for industrial and embedded products.
Performance, memory, and real‑time constraintsPower budget, thermal limits, and form factorOperating system, drivers, and ecosystemConnectivity, multimedia, and expansion needsSecurity, safety, and certification aspectsCost, lifecycle, and supply chain risksLesson 8PCB layout and hardware practices for noisy environments: grounding, star grounds, signal routing, common-mode chokes, and decouplingCovers PCB layout strategies for noisy and industrial environments, focusing on grounding schemes, star grounds, controlled signal routing, common‑mode chokes, and decoupling networks to minimize EMI, crosstalk, and ground bounce issues.
Ground planes, splits, and star ground patternsHigh‑speed and sensitive signal routing rulesPlacement of decoupling and bulk capacitorsUse of common‑mode chokes and ferrite beadsGuard traces, stitching vias, and return paths
