computer structure course
Gain mastery in CPU design for embedded and IoT devices. The course explores pipelines, caches, memory hierarchies, buses, interrupts, DMA, and low-power methods, enabling you to create faster, more efficient, and dependable tech solutions with practical insights into trade-offs and specifications.
from 4 to 360h flexible workload
valid certificate in your country
What will I learn?
This course offers a straightforward look at how modern CPUs are built, covering pipelines, register files, ALU design, caches, memory systems, buses, and memory-mapped I/O. You'll dive into interrupts, DMA, latency management, power-saving techniques, real-world compromises, timing analysis, and documentation to confidently design solid embedded systems.
Elevify advantages
Develop skills
- Design efficient low-power CPUs using RISC principles, pipelining, and clock gating for IoT applications.
- Optimise memory systems by selecting appropriate cache sizes, TCM, and DRAM for better performance and power use.
- Build reliable pipelines that manage hazards, branches, interrupts, and exceptions effectively.
- Implement I/O and DMA integration with peripheral mapping, ISR design, and reduced latency and power consumption.
- Define complete microarchitectures including buses, ALU, registers, and interfaces ready for RTL development.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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