computer structure course
Gain expertise in CPU design for embedded and IoT devices. The course explores pipelines, caches, memory hierarchies, buses, interrupts, DMA, and low-power techniques, enabling you to develop faster, more efficient, and dependable tech solutions with solid understanding of trade-offs and practical implementation.
flexible workload from 4 to 360h
valid certificate in your country
What will I learn?
This course offers a straightforward look at how modern CPUs are built, covering pipelines, register files, ALU design, caches, memory systems, buses, and memory-mapped I/O. You'll dive into interrupts, DMA, managing latency, power-saving methods, real-world design choices, timing analysis, and documentation to confidently create strong, efficient embedded systems.
Elevify advantages
Develop skills
- Design energy-efficient CPUs using RISC principles, pipelining, and clock gating for IoT applications.
- Optimise memory systems by selecting appropriate cache sizes, TCM, and DRAM for better performance and power use.
- Build reliable pipelines that manage hazards, branches, interrupts, and exceptions effectively.
- Implement I/O and DMA systems, including peripheral mapping, ISR design, to reduce latency and power consumption.
- Define complete microarchitectures with buses, ALU, registers, and interfaces ready for RTL development.
Suggested summary
Before starting, you can change the chapters and workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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