Lesson 1Calculating bandwidth and stability: closed-loop bandwidth from op-amp GBW, phase margin considerations, and compensation techniquesWe derive closed-loop bandwidth from op-amp gain-bandwidth product and feedback factor, then relate phase margin to stability and transient response. Compensation options for capacitive loads and high gains are introduced with design guidelines.
Relate GBW, feedback factor, and bandwidthInterpret Bode plots and phase margin targetsIdentify signs of marginal or unstable loopsDesign compensation for capacitive loadingCheck stability across process and temperatureLesson 2Practical component selection: finding and interpreting op-amp datasheets (examples of sensor-grade amplifiers)This section teaches how to read and compare op-amp datasheets for sensor conditioning. You will focus on noise, offset, input range, supply options, and packaging, and learn to screen parts quickly against system requirements.
Identify sensor-grade amplifier familiesInterpret input offset and drift specificationsEvaluate noise, CMRR, and PSRR parametersCheck input and output voltage rangesAssess package, power, and cost constraintsLesson 3SPICE simulation plan for amplifier block: stimulus sources (differential sine, common-mode, noise sources), AC analysis, transient, noise analysis, and offset/error measurementsThis section develops a structured SPICE plan for the amplifier block, defining stimuli, analyses, and measurements. You will learn how to verify gain, bandwidth, noise, offset, and common-mode behavior before committing to PCB layout.
Define simulation objectives and key metricsSet up differential and common-mode sourcesPlan AC, transient, and noise analysesMeasure gain, offset, and linearity in SPICEOrganize testbenches for reuse and reviewLesson 4Designing for input impedance: techniques to achieve high differential and common-mode input impedanceWe examine how to achieve high input impedance for differential and common-mode signals using op-amp input structures, buffer stages, and resistor choices, while controlling bias currents, leakage paths, and bandwidth limitations.
Define differential and common-mode impedanceUse buffer stages to isolate sensor loadingControl bias currents and leakage pathsGuarding and PCB techniques for high ZTrade-offs between impedance and bandwidthLesson 5Design documentation checklist: listing calculations, assumptions, part numbers, and margin analysis for PCB handoffThis section defines a rigorous documentation package for amplifier and sensor front-end designs, capturing calculations, assumptions, part choices, and margins so PCB, layout, and test teams can implement and review the circuit confidently.
List design assumptions and operating conditionsRecord key equations and intermediate calculationsDocument part numbers and critical parametersCapture margin analysis and derating choicesDefine required tests and acceptance criteriaLesson 6Op-amp key parameters and selection process: input noise density, input bias current, input offset, GBW, slew rate, CMRR, PSRR, and supply rangeWe review critical op-amp parameters for small-signal sensor interfaces and build a repeatable selection process. Emphasis is placed on noise density, bias current, GBW, slew rate, CMRR, PSRR, and supply range versus application needs.
Relate GBW and slew rate to signal bandwidthUnderstand input noise density and filtersBias current and source impedance interactionCMRR, PSRR, and supply rejection needsStep-by-step op-amp selection checklistLesson 7Resistor networks and gain calculation for differential amplifiers and instrumentation amps: deriving gain equations and loading effectsWe derive gain equations for classic differential and instrumentation amplifier topologies, including resistor network constraints and loading. Emphasis is placed on matching, CMRR, and how sensor and ADC impedances alter effective gain.
Gain equations for basic differential stagesThree-op-amp instrumentation amp gain designImpact of resistor matching on CMRR and gainLoading from sensor and ADC input impedanceSelecting resistor values and power ratingsLesson 8Setting amplifier target specifications: gain, bandwidth, input impedance, offset, drift, and noise budgetThis section shows how to translate system-level sensor requirements into amplifier targets for gain, bandwidth, input impedance, offset, drift, and noise. You will create a concise specification table to guide topology and part choices.
Translate sensor and ADC requirementsDefine gain, bandwidth, and headroom limitsSet input impedance and loading constraintsAllocate offset and drift performance goalsCreate a formal amplifier spec tableLesson 9Understanding differential sensor signals: source impedance, common-mode, and differential-mode conceptsThis section explains differential sensor behavior, including source impedance, common-mode level, and differential signal range. You will learn how these parameters affect noise, loading, and the choice of amplifier topology and reference scheme.
Define differential and common-mode componentsCharacterize sensor source impedance vs frequencyDetermine allowable common-mode voltage rangeRelate sensor specs to amplifier input limitsPlan cabling, shielding, and reference routingLesson 10Topology selection for small differential signals: instrumentation amplifier, differential amplifier, and difference-stage with front-end buffer — trade-offs and use casesThis section compares instrumentation amplifiers, classic differential amplifiers, and buffered difference stages for small differential signals. You will learn trade-offs in CMRR, noise, input range, cost, and layout complexity for each topology.
Review classic differential amplifier stageThree-op-amp instrumentation amplifier useBuffered difference stage with front-end gainCompare CMRR, noise, and input rangeGuidelines for topology selection by sensorLesson 11Offset and drift budgeting: calculating expected DC error from input offset, bias currents, resistor tolerances, and thermal effectsHere we build a quantitative DC error budget, combining op-amp offset, bias currents, resistor mismatch, and temperature drift. You will learn to allocate error limits, compute worst-case and RSS totals, and relate them to sensor accuracy.
Define DC accuracy and allowable error budgetModel input offset and bias current effectsInclude resistor tolerance and mismatch termsAccount for temperature coefficients and driftCompare worst-case versus RSS error methodsLesson 12Noise sources in low-level signals: Johnson noise, amplifier input-referred noise, and environmental interferenceWe identify and quantify noise sources in low-level sensor signals, including resistor thermal noise, amplifier input noise, and environmental interference. Techniques for modeling, budgeting, and reducing total noise are introduced.
Johnson noise of resistors and sensorsOp-amp voltage and current noise modelsInput-referred versus output noise conceptsEnvironmental and interference coupling pathsNoise budgeting and reduction strategiesLesson 13Expected simulation plots and measurements: gain vs frequency, phase, input-referred noise, output noise spectrum, transient response to 1 kHz sine, and worst-case offset scenariosThis section defines the key plots and measurements expected from simulation and bench work. You will connect Bode plots, noise spectra, transient responses, and offset sweeps to the original specifications and error budgets for the design.
Gain and phase versus frequency Bode plotsInput-referred and output noise spectraTransient response to sine and step inputsOffset versus common-mode and temperatureCompare simulated and measured performance
