Computer structure course
Gain mastery in CPU design for embedded and IoT devices. The course explores pipelines, caches, memory hierarchies, buses, interrupts, and energy-efficient techniques, enabling you to develop quicker, more reliable, and power-saving tech solutions with solid understanding of architecture trade-offs and practical implementation.
from 4 to 360h flexible workload
valid certificate in your country
What will I learn?
This course offers a straightforward look at how modern CPUs are built, covering pipelines, register files, ALU design, caches, memory systems, buses, and memory-mapped I/O. You'll dive into interrupts, DMA, managing latency, power-saving methods, real-world design choices, timing plans, and documentation to confidently create strong, efficient embedded systems.
Elevify advantages
Develop skills
- Design efficient low-power CPUs using RISC principles, pipelining, and clock gating for IoT applications.
- Optimise memory systems by selecting right sizes for caches, TCM, and DRAM to balance speed and power use.
- Build reliable pipelines that manage hazards, branches, interrupts, and exceptions effectively.
- Implement I/O and DMA systems, mapping peripherals, creating ISRs, and reducing latency and energy draw.
- Define complete microarchitectures including buses, ALU, registers, and interfaces ready for RTL development.
Suggested summary
Before starting, you can change the chapters and workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workloadWhat our students say
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