VLSI Physical Design Course
This course equips you with hands-on expertise in VLSI physical design, guiding you through transforming a 32-bit ALU from RTL handoff to final tapeout. You will explore floorplanning, placement, clock tree synthesis, routing, power integrity including IR drop control, timing optimisation, and comprehensive signoff checks such as STA, DRC, LVS, and reliability verification, enabling you to create high-performance chips suitable for advanced manufacturing nodes.
from 4 to 360h flexible workload
valid certificate in your country
What will I learn?
Gain practical skills in VLSI physical design, covering floorplanning, macro and IO placement, power grid setup, IR drop management, placement optimisation, clock tree synthesis, routing, and timing closure for a 32-bit pipelined ALU. Master essential signoff processes like static timing analysis, design rule checks, layout versus schematic verification, extraction, reliability analysis, and GDSII preparation to produce reliable chips ready for manufacturing.
Elevify advantages
Develop skills
- Master RTL to netlist handoff with import processes, sanity checks, and clean synthesis outputs.
- Excel in floorplanning including macro placement, IO setup, power grid design, and CMOS physical hierarchy.
- Optimise placement and CTS for congestion management and reliable 500 MHz clock trees.
- Ensure power integrity through IR drop analysis, decap strategies, and current density compliance.
- Achieve signoff readiness with STA, DRC/LVS checks, reliability verification, and production GDSII files.
Suggested summary
Before starting, you can change the chapters and workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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