from 4 to 360h flexible workload
valid certificate in your country
What will I learn?
This VLSI Physical Design Course provides a quick, hands-on journey from RTL handoff to tapeout. You'll learn floorplanning, macro and IO planning, power grid design, IR drop control, placement, CTS, routing, and timing closure for a 32-bit pipelined ALU. Gain expertise in signoff checks like STA, DRC, LVS, extraction, reliability, and final GDSII deliverables to confidently create efficient, manufacturable chips.
Elevify advantages
Develop skills
- Handle RTL to netlist handoff: import, sanity checks, and clean synthesis outputs.
- Master floorplanning: macro, IO, power grid, and physical hierarchy in CMOS.
- Perform placement and CTS: congestion-aware placement, robust 500 MHz clock trees.
- Ensure power integrity in practice: IR drop, decap planning, and current density limits.
- Achieve signoff confidence: STA, DRC/LVS, reliability checks, and fab-ready GDSII.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students are saying
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