Lesson 1Subroutine and stack operations: JSR/RTS, stack push/pop semantics and stack pointer conventionsThis section details subroutine call and return instructions, stack push and pop semantics, stack pointer updates, calling conventions, and how nested calls, interrupts, and reentrancy rely on a well defined stack model.
JSR and call instruction behaviorRTS and return address handlingPush and pop data formatsStack pointer growth directionCalling conventions and framesInteraction with interruptsLesson 2Arithmetic and logic instructions: ADD, SUB, AND, OR, CMP with flag behavior and carry/borrow handlingThis section covers arithmetic and logic instructions such as ADD, SUB, AND, OR, and CMP, detailing flag behavior, carry and borrow handling, signed versus unsigned interpretation, and overflow detection strategies.
ADD and SUB operation semanticsLogical AND, OR, XOR behaviorCompare and test instructionsCarry, borrow, and overflow flagsSigned versus unsigned resultsLesson 3Designing concise mnemonics and operand encoding for clarity and implementabilityThis section covers how to craft readable mnemonics and operand formats that map cleanly to hardware, balancing orthogonality, encoding density, decode simplicity, and long term extensibility of the instruction set.
Choosing consistent mnemonic namingOperand order and syntax conventionsEncoding opcode fields and subfieldsBalancing orthogonality and complexityExtensibility for future instructionsLesson 4Minimum opcode encoding: opcodes, operand bytes, instruction sizes and example encoding schemesThis section focuses on compact opcode encodings, separating opcode and operand bytes, using prefix or extension schemes, and illustrating tradeoffs between dense encodings, decode complexity, and future scalability.
Opcode field width selectionOperand specifier encodingPrefix and escape opcode schemesVariable length instruction formatsExamples of compact encodingsLesson 5Instruction class taxonomy: data movement, arithmetic/logic, control flow, stack/subroutine, and I/OThis section classifies instructions into data movement, arithmetic and logic, control flow, stack and subroutine, and I/O groups, showing how a clear taxonomy aids documentation, decoding, and compiler backend design.
Data movement instruction groupArithmetic and logic instruction groupControl flow and branch groupStack and subroutine instruction groupI/O and system instruction groupLesson 6Instruction timing and size table: how to decide instruction byte length and execution cyclesThis section describes how to assign instruction byte lengths and cycle counts, relating bus width, memory system, and microarchitecture to timing tables that guide programmers, toolchains, and performance tuning.
Factors affecting instruction sizeCycle components and microstepsTiming tables for each addressing modeImpact of caches and wait statesUsing timing data for optimizationLesson 7Addressing modes: immediate, direct (zero-page/data), absolute, indirect, register, and impliedThis section explores common addressing modes, including immediate, direct or zero page, absolute, indirect, register, and implied, explaining encoding patterns, effective address calculation, and typical use cases.
Immediate literal operandsDirect or zero page addressingAbsolute and extended addressingIndirect and indexed addressingRegister and implied modesLesson 8Control flow instructions: JMP, conditional branches (BEQ/BNE/BC/BN), relative vs absolute addressing and their rangeThis section analyzes control flow instructions such as jumps and conditional branches, comparing relative and absolute addressing, encoding branch ranges, and handling pipeline effects like delay slots or branch prediction.
Unconditional jump encodingsConditional branch condition setRelative versus absolute targetsBranch range and offset sizingInteraction with pipelinesLesson 9I/O and memory-mapped access instructions: IN/OUT or mapped loads/stores and side-effect considerationsThis section explains I/O instructions and memory mapped access, including IN and OUT style ports, mapped load and store behavior, ordering and timing constraints, and how to document side effects visible to software.
Isolated versus memory mapped I/OIN and OUT instruction semanticsI/O timing and wait state handlingSide effects and volatile semanticsAtomicity and ordering guaranteesLesson 10Data move instructions: LDA/STA equivalents, supported modes, effects on flags and cyclesThis section examines load and store style instructions, supported addressing modes, interaction with condition flags, and how cycle counts and bus activity differ between register, memory, and special data move operations.
Accumulator and register load formsStore instructions and memory side effectsSupported addressing modes for movesFlag behavior on loads and storesCycle counting for move variants
