VLSI Physical Design Course
This course offers hands-on training in VLSI physical design, covering the full flow from RTL to tapeout for a 32-bit pipelined ALU, including floorplanning, placement, CTS, routing, power management, and signoff checks to produce manufacturable chips.
flexible workload of 4 to 360h
valid certificate in your country
What will I learn?
This VLSI Physical Design Course provides a quick, hands-on route from RTL handover to tapeout. You will learn floorplanning, macro and IO planning, power grid design, IR drop management, placement, CTS, routing, and timing closure for a 32-bit pipelined ALU. Gain expertise in signoff checks such as STA, DRC, LVS, extraction, reliability, and final GDSII outputs to confidently create efficient, manufacturable chips.
Elevify advantages
Develop skills
- RTL to netlist handover: importing, sanity checks, and cleaning synthesis outputs.
- Floorplanning expertise: macro, IO, power grid, and physical hierarchy in CMOS.
- Placement and CTS: congestion-aware placement, robust 500 MHz clock trees.
- Power integrity in action: IR drop, decap planning, and current density limits.
- Signoff assurance: STA, DRC/LVS, reliability checks, and fab-ready GDSII.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workloadWhat our students say
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