VLSI Physical Design Course
This course covers the complete VLSI physical design flow from RTL to tapeout, focusing on practical implementation for a 32-bit pipelined ALU, including floorplanning, placement, CTS, routing, power integrity, and signoff checks to produce manufacturable chips.
4 to 360 hours flexible workload
valid certificate in your country
What will I learn?
This VLSI Physical Design Course provides a swift, practical route from RTL handoff to tapeout. Learn floorplanning, macro and IO planning, power grid design, IR drop control, placement, CTS, routing, and timing closure for a 32-bit pipelined ALU. Master signoff checks including STA, DRC, LVS, extraction, reliability, and final GDSII deliverables so you can confidently build efficient, manufacturable chips.
Elevify advantages
Develop skills
- RTL to netlist handoff: import, sanity checks, and clean synthesis outputs.
- Floorplanning mastery: macro, IO, power grid, and physical hierarchy in CMOS.
- Placement and CTS: congestion-aware placement, robust 500 MHz clock trees.
- Power integrity in practice: IR drop, decap planning, and current density limits.
- Signoff confidence: STA, DRC/LVS, reliability checks, and fab-ready GDSII.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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