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VLSI Chip Design Course
Bula bokgoni jwa tiro ya gago ya boitlhamedi ka Khooso ya rona ya Go Dira Di-Chip tsa VLSI. Ithute botlhokwa jwa go dira di-VLSI, o itsenye mo tsamaisong ya memori, kgokagano, le go dira di-interface. Sekaseka didirisiwa tsa segompieno tsa VLSI CAD, mekgwa ya go etsisa, le go tshwara disheme. Tokafatsa bokgoni jwa gago mo go somareng maatla, tokafatso ya tiragatso, le ditokumente tsa botegeniki. Khooso e e maemo a a kwa godimo e, e e itebagantseng le go dira, e diretswe batho ba ba dirang go bona bokgoni mo lefatsheng le le tsamayang ka bofefo la go dira di-chip. Ikwadise jaanong go fetola bokgoni jwa gago.
- Itseng mananeo a memori: Tokafatsa dipopego tsa memori ya VLSI go bona bokgoni.
- Dira di-interface tsa on-chip: Tlhabolola diprothokholo tsa tlhaeletsano tse di nonofileng le maemo a I/O.
- Dirisa didirisiwa tsa VLSI CAD: Diragatsa go tshwara disheme le go baya dipopego ka nepo.
- Tsenya tirisong maano a maatla: Dirisa mekgwa ya maatla a a kwa tlase go dira di-chip ka bokgoni.
- Tokafatsa tiragatso: Oketsa lebelo ka go dirisa diphaephe le go dira diprothokholo ka go bapisa.
from 4 to 360h flexible workload
certificate recognized by MEC
What will I learn?
Bula bokgoni jwa tiro ya gago ya boitlhamedi ka Khooso ya rona ya Go Dira Di-Chip tsa VLSI. Ithute botlhokwa jwa go dira di-VLSI, o itsenye mo tsamaisong ya memori, kgokagano, le go dira di-interface. Sekaseka didirisiwa tsa segompieno tsa VLSI CAD, mekgwa ya go etsisa, le go tshwara disheme. Tokafatsa bokgoni jwa gago mo go somareng maatla, tokafatso ya tiragatso, le ditokumente tsa botegeniki. Khooso e e maemo a a kwa godimo e, e e itebagantseng le go dira, e diretswe batho ba ba dirang go bona bokgoni mo lefatsheng le le tsamayang ka bofefo la go dira di-chip. Ikwadise jaanong go fetola bokgoni jwa gago.
Elevify advantages
Develop skills
- Itseng mananeo a memori: Tokafatsa dipopego tsa memori ya VLSI go bona bokgoni.
- Dira di-interface tsa on-chip: Tlhabolola diprothokholo tsa tlhaeletsano tse di nonofileng le maemo a I/O.
- Dirisa didirisiwa tsa VLSI CAD: Diragatsa go tshwara disheme le go baya dipopego ka nepo.
- Tsenya tirisong maano a maatla: Dirisa mekgwa ya maatla a a kwa tlase go dira di-chip ka bokgoni.
- Tokafatsa tiragatso: Oketsa lebelo ka go dirisa diphaephe le go dira diprothokholo ka go bapisa.
Suggested summary
Before starting, you can change the chapters and the workload. Choose which chapter to start with. Add or remove chapters. Increase or decrease the course workload.What our students say
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