Chip Design Course

Lesson 1 • Sequential Logic and State Machines

Introduces flip-flops, registers, and finite state machines. Provides the timing and state concepts required for RTL design.

Lesson 2 • Binary Systems and Boolean Algebra

Covers number systems, logic gates, and Boolean simplification. Establishes the mathematical language used throughout all chip design workflows.

Lesson 3 • VLSI Technology Overview

Surveys CMOS transistor operation, scaling trends, and chip abstraction layers. Frames the physical context for all subsequent design work.

Lesson 1 • RTL Coding Guidelines and Lint

Establishes style rules, naming conventions, and lint-clean coding practices. Ensures RTL is readable, maintainable, and synthesis-ready.

Lesson 2 • Procedural Blocks and Operators

Covers always blocks, if-else, case statements, and operators. Enables writing behavioural RTL that maps cleanly to hardware.

Lesson 3 • RTL Design of Common Modules

Applies HDL skills to design FIFOs, counters, and state machines. Reinforces coding patterns that synthesise to efficient hardware.

Lesson 4 • HDL Syntax and Data Types

Introduces module structure, port declarations, and data types. Correct syntax usage is the prerequisite for all RTL coding tasks.

Lesson 1 • Verification Planning and Methodology

Defines verification goals, test plans, and coverage metrics. Aligns verification effort with design risk before writing any code.

Lesson 2 • Assertion-Based Verification

Introduces immediate and concurrent assertions, sequences, and properties. Catches protocol violations automatically during simulation.

Lesson 3 • Functional Coverage Collection

Teaches covergroups, coverpoints, and cross coverage. Provides quantitative proof that the verification plan has been exercised.

Lesson 4 • UVM Testbench Architecture

Explains UVM components, phases, and TLM connections. Provides a reusable, scalable framework for block and system verification.

Lesson 1 • Static Timing Analysis Basics

Introduces setup and hold analysis, timing paths, and slack interpretation. Provides the analytical foundation for timing closure in later chapters.

Lesson 2 • Synthesis Flow and Tool Setup

Covers the RTL-to-netlist flow, technology library loading, and tool invocation. Establishes the synthesis environment before applying any optimisations.

Lesson 3 • Timing Constraints with SDC

Teaches clock definition, input/output delays, and multicycle paths using SDC syntax. Correct constraints drive all timing-driven optimisations.

Lesson 4 • Gate-Level Netlist Verification

Covers formal equivalence checking and gate-level simulation. Confirms that synthesis preserved RTL intent before physical design begins.

Lesson 1 • Macro Placement Strategies

Covers hard macro placement rules, channel creation, and feedthrough planning. Good macro placement minimises routing congestion and timing risk.

Lesson 2 • Floorplan Validation and Sign-Off

Runs DRC, connectivity checks, and timing estimates on the floorplan. Catches structural issues before placement consumes significant runtime.

Lesson 3 • Physical Design Flow Overview

Maps the end-to-end physical design stages from netlist to GDSII. Contextualises floorplanning within the full implementation flow.

Lesson 4 • Die Size and Aspect Ratio Selection

Teaches utilisation estimation, die sizing, and aspect ratio trade-offs. Correct die sizing prevents congestion and timing failures downstream.

Lesson 1 • Clock Tree Synthesis

Builds a balanced clock distribution network meeting skew and insertion-delay targets. CTS quality determines hold margin and power consumption.

Lesson 2 • Pre-CTS Timing Optimisation

Applies buffer insertion, gate sizing, and logic restructuring before clock tree synthesis. Fixes setup violations whilst clock skew is still ideal.

Lesson 3 • Global and Detailed Routing

Executes routing in two stages to resolve congestion and meet DRC rules. Routing completion is required before parasitic extraction.

Lesson 4 • Standard-Cell Placement

Covers global and detailed placement algorithms, congestion-driven placement, and timing-driven placement. Placement quality directly determines routing success.

Lesson 1 • Power Analysis and Sign-Off

Computes dynamic and leakage power using switching activity and SPEF data. Power sign-off confirms thermal and battery-life targets are met.

Lesson 2 • Advanced Timing Constraint Closure

Addresses complex constraints including generated clocks, clock domain crossings, and interface timing. Resolves constraint gaps that cause false sign-off.

Lesson 3 • Multi-Corner Multi-Mode STA

Runs timing analysis across PVT corners and functional modes simultaneously. Ensures the design meets timing under all operating conditions.

Lesson 4 • RC Parasitic Extraction Fundamentals

Explains resistance and capacitance extraction models, corners, and SPEF format. Accurate parasitics are the foundation of credible sign-off analysis.

Lesson 1 • GDSII Preparation and Tapeout

Merges all layout views, applies final checks, and streams out GDSII to the foundry. Tapeout is the final irreversible step in the design cycle.

Lesson 2 • Electrical Rule Checking

Identifies floating nodes, antenna violations, and electromigration risks in the layout. ERC catches reliability issues not covered by DRC or LVS.

Lesson 3 • Layout Versus Schematic Verification

Compares extracted netlist to schematic netlist to confirm connectivity. LVS errors indicate wiring mistakes that would cause silicon failure.

Lesson 4 • Design Rule Checking

Executes DRC using foundry rule decks and interprets violation categories. DRC clean-up is mandatory before any layout is submitted for fabrication.